A 0.18 μm flash source side erasing improvement

Author

Laffont, R. ; Bouchakour, R. ; Pizzuto, O. ; Mirabel, J.M.

Author_Institution

L2MP-Polytech, UMR-CNRS, Marseille, France

fYear

2004

fDate

15-17 Nov. 2004

Firstpage

105

Lastpage

109

Abstract

The aim of this work is to present two solutions developed to optimize Flash cell erasing time. These solutions have been proposed with our flash simulator based on Pao and Sah approach. This model was implemented in a common circuit simulator, Eldo, and used to study the Flash memory writing/erasing operations. Thank to simulations, we have proposed two solutions to increase injection efficiency of the cell during erasing operation. The first solution is based on signal optimization and the second on a simple process modification during SAS etching. These two solutions have been validated with ST-Microelectronics Flash technologies.

Keywords

circuit optimisation; circuit simulation; flash memories; Eldo; Flash technologies; Pao and Sah approach; SAS etching; ST-Microelectronics; circuit simulator; erase optimization; flash memory; flash simulator; flash source side erasing improvement; process modification; signal optimization; writing/erasing operations; Capacitance; Circuit simulation; Energy consumption; Flash memory; MOSFET circuits; Nonvolatile memory; Random access memory; Tunneling; Voltage; Writing;

fLanguage

English

Publisher

ieee

Conference_Titel

Non-Volatile Memory Technology Symposium, 2004

Print_ISBN

0-7803-8726-0

Type

conf

DOI

10.1109/NVMT.2004.1380815

Filename

1380815