A 10-Gb/s fully balanced differential output transimpedance amplifier in 0.18-μm CMOS technology for SDH/SONET application

In this paper, a fully balanced 10-Gb/s differential output transimpedance amplifier (TIA) is realized in 0.18-mum CMOS technology for SDH/SONET application. The TIApsilas input dynamic range is further improved by adding an automatic gain control (AGC) amplifier circuit. To extend the -3-dB bandwidth in a limited 0.18-mum CMOS process, this design utilizes the series peaking technique with 50-Omega output buffer while achieves the differential gain of 62-dBOmega and the bandwidth of 8.1-GHz in the presence of 0.2-pF photodiode capacitance. This TIA operates from a dual supply voltages of 1.8-V for TIA core and 2.2-V for the AGC block while consuming 70-mW of total chip power with the input sensitivity of -15-dBm for a bit error ratio (BER) of 10^-12.