DocumentCode
2325542
Title
An Optimized Scalable and Unified Hardware Structure of Montgomery Multiplier
Author
Yang Xiao-Hui ; Qin Fan ; Zhang Jun ; Dai Zi-bin ; Zhang Yong-fu
Author_Institution
Inst. of Electron. Technol., PLA Inf. Eng. Univ., Zhengzhou, China
fYear
2009
fDate
23-24 May 2009
Firstpage
1
Lastpage
5
Abstract
Modular multiplication is the core operation of ECC (Elliptic Curve Cryptosystems). Based on the Montgomery multiplication algorithm, a scalable and unified modular multiplier is proposed which can work with any precision of the operands and work in both prime and binary finite fields at the same time. It is captured in Verilog and synthesized under 0.18 mum CMOS technology. The result indicates that this work can achieve high clock frequency and perform efficiently than other works as the clock numbers are reduced greatly.
Keywords
multiplying circuits; public key cryptography; CMOS technology; Montgomery modular multiplication algorithm; Verilog; binary finite field; elliptic curve cryptosystem; prime finite field; size 0.18 mum; unified hardware structure; Application specific integrated circuits; Arithmetic; CMOS technology; Clocks; Elliptic curve cryptography; Galois fields; Hardware; Polynomials; Public key; Public key cryptography;
fLanguage
English
Publisher
ieee
Conference_Titel
E-Business and Information System Security, 2009. EBISS '09. International Conference on
Conference_Location
Wuhan
Print_ISBN
978-1-4244-2909-7
Electronic_ISBN
978-1-4244-2910-3
Type
conf
DOI
10.1109/EBISS.2009.5137928
Filename
5137928
Link To Document