Teaching IC design, layout, and testing through a university-industry cooperative venture

Students and faculty at Georgia Tech design, simulate, layout, and design-rule-check CMOS integrated circuits for fabrication at Harris Corp.. Circuits designed in this way become part of a multiproject chip. Harris engineers also design-rule-check all circuits, fabricate the ICs, and return wafers to Georgia Tech. Students test circuits both at the wafer level and at the package level after dicing and bonding. Project results are summarized in student reports made available to Harris. Objectives of the program are described and the factors that have contributed to the success of this activity are detailed. A typical project is discussed to illustrate how this project has served as the stimulation and motivation for student and faculty education