Efficient cell characterization for SSTA

Statistical static timing analysis(SSTA) is an emerging technique that addresses increasing process variation effects on circuit behavior for designs at 65 nm and below. SSTA offers a number of advantages over traditional corner based static timing analysis(STA), most notably it provides a more realistic estimation of timing relative to actual silicon performance. Accurate statistical timing analysis needs accurate statistical cell models, which in turn requires a new approach to cell library characterization. A statistical cell characterization system must adequately capture the effects of variation, while simultaneously maintaining fast turnaround time to avoid being the bottleneck in the statistical analysis flow. In this paper, we review various issues in statistical timing analysis. We also describe an efficient library characterization methodology which can reduce the time needed to construct statistical cell library using interpolation.