A scalable distributed memory architecture for Network on Chip

Besides processors, DSPs and other IP blocks, Network on Chip (NoC) also integrates lots of memories. However, the research of on chip memory subsystem for NoC has not been undertaken thoroughly. In this paper, a distributed None Uniform Memory Access (NUMA) memory architecture for NoC is developed; the performance and the programming mode of this system are discussed. Two kinds of parallel algorithms are implemented, the pipelined matrix multiplication and the full-parallel FFT. Simulation results verify the proposed architecture can achieve high parallelism and provide flexible programming scheme.