Formal verification for microprocessors with extendable instruction set

The correctness of processors is a key for their application. Although some verification methods were developed and successfully applied to conventional microprocessors, only a few of them were used in the context of application specific devices. This work introduces a formal verification approach for a reconfigurable microprocessor with extendable instruction set. The application of this approach is demonstrated using register transfer description of the CoMPARE processor and the Stanford Validity Checker as prover. Some undesired side effects of different instructions that were not discovered during the simulation were found by the verification process. In addition some deficiencies of the hardware description notation as specification formalism were shown