RaceCheck: A race logic audit program for ESL-based soc designs

This paper describes a new version of RaceCheck, an advanced static and dynamic race logic analysis program, that can audit a new type of race logic arises from the use of inter-process communication (IPC) objects in electronic system level (ESL) based system-on-chip (SoC) designs. As the use of IPC objects to synchronize concurrent processes and to pass messages among them is new to most SoC designers, it is expected race logic involving those IPC objects will also be common on large-scale SoC circuits, and these race logic are not audited by any EDA tools. This paper describes the IPC objects and the methods to audit the race logic involving those IPC objects in SoC circuits. RaceCheck complements other advanced design verification tools to aid users to achieve 100% functional coverage of their new SoC products and time-to-market.