A 108 Gbps, 1.5 GHz 1D-DCT architecture

Author

Shams, Ahmed ; Bayoumi, Magdy

Author_Institution

Center for Adv. Comput. Studies, Louisiana Univ., Lafayette, LA, USA

fYear

2000

fDate

2000

Firstpage

163

Lastpage

172

Abstract

A high-performance ID-DCT architecture is proposed. It is based on the New Distributed Arithmetic Architecture algorithm (NEDA). Enhancements to NEDA are proposed to reduce the number of computations. Only addition operations are used, with 42 additions to compute the outputs for a 8×1 DCT. No subtractions, multiplications, or ROM are needed. High-throughput is achieved by pipelining the architecture. In every clock cycle, it receives eight pixels (each is 9-bits) as inputs, and produces eight DCT coefficients (each is 14-bits). The delay of one pipeline stage is the delay of a 3-level 4:2 compressor tree. The architecture is implemented in 0.35 μm technology; it runs at 1.5 GHz, and processes 108 Gbps of image/video sequence data

Keywords

CMOS digital integrated circuits; VLSI; data compression; digital signal processing chips; discrete cosine transforms; distributed arithmetic; high-speed integrated circuits; image coding; parallel algorithms; parallel architectures; video coding; 0.35 micron; 1.5 GHz; 108 Gbit/s; 1D-DCT architecture; 3-level 4:2 compressor tree; CMOS VLSI implementation; DCT coefficients; DSP chip; NEDA algorithm enhancements; New Distributed Arithmetic Architecture algorithm; addition operations; architecture pipelining; high-throughput; Computer architecture; Discrete cosine transforms; Discrete transforms; Frequency domain analysis; Image coding; Image storage; Karhunen-Loeve transforms; Transform coding; Video compression; Videoconference;

fLanguage

English

Publisher

ieee

Conference_Titel

Application-Specific Systems, Architectures, and Processors, 2000. Proceedings. IEEE International Conference on

Conference_Location

Boston, MA

ISSN

2160-0511

Print_ISBN

0-7695-0716-6

Type

conf

DOI

10.1109/ASAP.2000.862387

Filename

862387