Scalable and parallel codec architectures for the DVB-S2 FEC system

The recent Digital Video Satellite Broadcast Standard (DVB-S2) has adopted a powerful FEC scheme based on the serial concatenation of Bose-Chaudhuri-Hocquenghen (BCH) and low-density parity-check (LDPC) codes. The high-speed requirements, long block lengths and adaptive encoding defined in the DVB-S2 standard, present complex challenges in the design of an efficient codec hardware architecture. In this paper, synthesizable, high throughput, scalable and parallel HDL models supporting the 21 different BCH+LDPC DVB-S2 code configurations are presented. For BCH decoding, an efficient Chien search circuit for shortened BCH codes is proposed. The LDPC codec architecture explores the periodicity M = 360 of the special LDPC-IRA codes adopted by the standard. Synthesis results for an FPGA device from Xilinx show a throughput above the minimal 90 Mbps.