Designing ultra-low voltage PLL Using a bulk-driven technique

This paper describes an ultra-low voltage phase-locked loop (PLL) using a bulk-driven technique. The architecture of the proposed PLL employs the bulk-input technique to produce a voltage-controlled oscillator (VCO) and the forward-body-bias scheme to produce a divider. This approach effectively reduces the threshold voltage of the MOSFETs, enabling the PLL to be operated at an ultra-low voltage. The chip is fabricated in a 0.13-mum standard CMOS process with a 0.5 V power supply voltage. The measurement results demonstrate that this PLL can operate from 360 to 610 MHz with a 0.5 V power supply voltage. At 550 MHz, the measured rms jitter and peak-to-peak jitter are 8.01 ps and 56.36ps, respectively. The total power consumption of the PLL is 1.25 mW and the active die area of PLL is 0.04 mm².