Low-complexity shift-LDPC decoder for high-speed communication systems

In this paper, an efficient high-speed low-density parity-check (LDPC) decoder is presented. Single minimum decoding and non-uniform quantization schemes are explored to reduce the complexity of computation core and the memory requirement. Shifting structure is incorporated to significantly reduce the routing complexity of the LDPC decoder. The implementation of an 8192-bit LDPC decoder demonstrates that about 63.3% hardware reduction can be achieved compared with the state-of-the-art design for high speed LDPC decoding. It is also shown that, using SMIC 0.18 mum CMOS technology, 5.4 Gb/s decoding throughput can be obtained at 15 decoding iterations.