A user configurable gate array using CMOS-EPROM technology

Author

Gupta, Anil ; Aggarwal, Vinita ; Patel, Rakesh ; Chalasani, Prasad ; Chu, Dante ; Seeni, Paramesh ; Liu, Pin-Wu ; Wu, John ; Kaat, Gerrit

Author_Institution

Philips Components-Signetics, Sunnyvale, CA, USA

fYear

1990

fDate

13-16 May 1990

Abstract

A 68-pin programmable gate array, implemented in 1-μm CMOS-EPROM technology, is described. Input-to-output delay of 20 ns for single-level logic is achieved for an array of 258 input lines X 199 product terms. Architecture with 96 NAND foldbacks allows multilevel logic capability. The die size is 55.3 Kmil², and a power-down option is provided. In addition to the main array there is a clock array which generates 10 internal clocks for 10 of the buried JK flip-flops. A scan mode is implemented to offer additional testability of the flip-flops

Keywords

CMOS integrated circuits; PROM; VLSI; logic arrays; 1 micron; 20 ns; CMOS-EPROM technology; NAND foldbacks; PLD; buried JK flip-flops; clock array; die size; internal clocks; multilevel logic capability; power-down option; programmable gate array; programmable logic devices; scan mode; single-level logic; testability; user configurable gate array; CMOS logic circuits; CMOS technology; Circuit testing; Clocks; Flip-flops; Logic arrays; Logic devices; Logic testing; Programmable logic arrays; Programmable logic devices;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 1990., Proceedings of the IEEE 1990

Conference_Location

Boston, MA

Type

conf

DOI

10.1109/CICC.1990.124846

Filename

124846