• DocumentCode
    2330851
  • Title

    Efficient multi-layer obstacle-avoiding rectilinear steiner tree construction

  • Author

    Lin, Chung-Wei ; Huang, Shih-Lun ; Hsu, Kai-Chi ; Li, Meng-Xiang ; Chang, Yao-Wen

  • Author_Institution
    Nat. Taiwan Univ., Taipei
  • fYear
    2007
  • fDate
    4-8 Nov. 2007
  • Firstpage
    380
  • Lastpage
    385
  • Abstract
    Given a set of pins and a set of obstacles on routing layers, a multi-layer obstacle-avoiding rectilinear Steiner minimal tree (ML-OARSMT) connects these pins by rectilinear edges within layers and vias between layers, and avoids running through any obstacle to construct a Steiner tree with a minimal total cost. The ML-OARSMT problem is very important for many VLSI designs with pins being located in multiple routing layers that contain numerous routing obstacles incurred from IP blocks, power networks, prerouted nets, etc. Therefore, it is desired to develop an effective algorithm for the ML-OARSMT problem. However, there is no existing work on this ML-OARSMT problem. In this paper, we first formulate the ML-OARSMT problem and identify key different properties of the problem from its single-layer counterpart. Based on the multilayer obstacle-avoiding spanning graph (ML-OASG), we present the first algorithm to solve the ML-OARSMT problem. Our algorithm can guarantee an optimal solution for any 2-pin net and many higher-pin nets. Experiments show that our algorithm results in 33% smaller total costs on average than a construction-by-correction heuristic which is widely used for Steiner-tree construction in the recent literature.
  • Keywords
    VLSI; circuit complexity; circuit optimisation; integrated circuit design; network routing; network topology; trees (mathematics); IP blocks; VLSI design; multilayer obstacle-avoidance; pin connection; power network; prerouted nets; rectilinear Steiner minimal tree; rectilinear edges; routing layer; routing obstacles; spanning graph; Costs; Delay; Manufacturing; NP-complete problem; Nonhomogeneous media; Pins; Routing; Steiner trees; Timing; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer-Aided Design, 2007. ICCAD 2007. IEEE/ACM International Conference on
  • Conference_Location
    San Jose, CA
  • ISSN
    1092-3152
  • Print_ISBN
    978-1-4244-1381-2
  • Electronic_ISBN
    1092-3152
  • Type

    conf

  • DOI
    10.1109/ICCAD.2007.4397294
  • Filename
    4397294