• DocumentCode
    2331471
  • Title

    Analog placement with common centroid constraints

  • Author

    Ma, Qiang ; Young, Evangeline F Y ; Pun, K.P.

  • Author_Institution
    Chinese Univ. of Hong Kong, Kowloon
  • fYear
    2007
  • fDate
    4-8 Nov. 2007
  • Firstpage
    579
  • Lastpage
    585
  • Abstract
    In order to reduce parasitic mismatch in analog circuits, some groups of devices are required to share a common centroid while being placed. Devices are split into smaller ones and placed with a common center point. We will address this problem of handling common centroid constraint in placement. A new representation called center-based corner block list (C-CBL) is proposed which is a natural extension of corner block list (CBL) [1] to represent a common centroid placement of a set of device pairs. C-CBL is complete and non-redundant in representing any common centroid mosaic packings with pairs of blocks to be matched. To address the same problem with an additional constraint that devices are required to be placed uniformly to average out the parasitic errors, a grid-based approach is proposed. Experimental results show that both approaches are fast and promising, and have high scalability that even large data sets can be handled effectively.
  • Keywords
    analogue circuits; logic design; system-on-chip; analog circuit placement; center-based corner block list; common centroid constraint; parasitic mismatch; system-on-chip design; Analog circuits; Capacitors; Circuit optimization; Computer science; Data structures; Degradation; Resistors; Scalability; Simulated annealing; Threshold voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer-Aided Design, 2007. ICCAD 2007. IEEE/ACM International Conference on
  • Conference_Location
    San Jose, CA
  • ISSN
    1092-3152
  • Print_ISBN
    978-1-4244-1381-2
  • Electronic_ISBN
    1092-3152
  • Type

    conf

  • DOI
    10.1109/ICCAD.2007.4397327
  • Filename
    4397327