Circuit characteristic analysis considering NBTI and PBTI-induced delay degradation

Author

Yabuuchi, Michitarou ; Kobayashi, Kazutoshi

Author_Institution

Dept. of Electron., Kyoto Inst. of Technol., Kyoto, Japan

fYear

2012

fDate

9-11 May 2012

Firstpage

1

Lastpage

2

Abstract

Bias Temperature Instability (BTI) becomes one of the most important reliability issues for nanometer process devices. We focus on aging degradation by BTI because it is known as one of the dominant factor that determines life time of circuits. In this paper, we show circuit delay degradation characteristic of BTI using the circuit simulation. The delay increase 15% after 10 years stress.

Keywords

CMOS logic circuits; ageing; circuit simulation; integrated circuit reliability; logic gates; CMOS inverter; NBTI; PBTI-induced delay degradation; PMOS transistor; aging degradation; circuit characteristic analysis; circuit delay degradation characteristic; circuit life time; circuit simulation; logic circuit; nanometer process device; negative bias temperature instability; positive bias temperature instability; reliability issue; CMOS integrated circuits; Degradation; Delay; Delay effects; Integrated circuit modeling; Inverters; MOSFETs; BTI; aging degradation; reliability;

fLanguage

English

Publisher

ieee

Conference_Titel

Future of Electron Devices, Kansai (IMFEDK), 2012 IEEE International Meeting for

Conference_Location

Osaka

Print_ISBN

978-1-4673-0837-3

Type

conf

DOI

10.1109/IMFEDK.2012.6218587

Filename

6218587