Development of a behavioral model of the single-electron transistor for hybrid circuit simulation

The heterogeneous integration between CMOS devices and different emerging nanotechnologies such as the single-electronics tries to take the best of each technology. On one hand, the advantages of MOSFET devices are high speed and high current and the relative maturity of fabrication technology. On other hand, single-electronic technologies have the potencial to create high-density devices and have ultralow power consumption. The circuits composed by MOSFET and single-electronic devices are called hybrid circuits. The most representative structure of the single-electronic devices is the Single-Electron Transistor (SET), it is a three terminal architecture. This work develops a behavioral model that includes the gate capacitance parameter (C_G), that is one of the most important in the SET. The model has been developed to be used in a SPICE-like simulator as a user-defined model. Comparing the simulation results between our model and device-level simulator shows a high degree of agreement. The authors offer an analysis of the optimization for the biasing over hybrid and only-SET structures, as well as a parameter variations on the C_G for the SET.