Evaluation of susceptibility of FPGA-based circuits to fault injection attacks based on clock glitching

We present a method and tool for examining an FPGA-based circuit, in particular an implementation of a cryptographic algorithm, subjected to a fault injection attack based on clock glitching. The proposed approach offers some unique features that allow us to thoroughly analyse the impact of injected faults on the operation of the circuit. In particular, through precise adjustment of the frequency of an external clock generator, the number of faults occurring at the output of the circuit under test can be observed and controlled. The effectiveness of the proposed approach has been assessed for the AES implementation, leading to a number of practical guidelines that may be essential when planning experimental studies on fault injection in FPGA-based circuits.