Methodology for electromigration signoff in the presence of adaptive voltage scaling

Electromigration (EM) is a growing reliability concern in sub-22nm technology. Design teams must apply guardbands to meet EM lifetime requirements, at the cost of performance and power. However, EM lifetime analysis cannot ignore front-end reliability mechanisms such as bias temperature instability (BTl). Although the gate delay degradation due to BTI can be compensated by adaptive voltage scaling (AVS), nay elevated supply voltage will accelerate EM degradation and reduce lifetime. Since the degradation of BTI is front-loaded, AVS can increase electrical stress on metal wires relatively early during IC lifetime, which can significantly decrease electromigration reliability. In this paper, we study the "chicken-egg" interlock among BTI, AVS and EM and quantify timing and power costs of meeting EM lifetime requirements with full consideration of BTI and AVS mechanisms. By applying existing statistical and physical EM models, we demonstrate that without such considerations, the inaccuracy (reduction) of EM lifetime due to improper guardband against BTI at signoff can be as high as 30% in a 2Snm FDSOI foundry technology. Furthermore, we provide signoff guidelines which suggest that the lifetime penalty can be compensated by paying a penalty of up to 1.6% in area and 6% in power. We also demonstrate that suboptimal choice of voltage step size and scheduling strategy can result in up to 1.5 years of decreased EM lifetime.