Design of multicast packet switches for high-speed multi-service networks

The paper describes a multicast switch architecture for multi service networks that supports multi destination packet delivery at high data transfer rates (/spl ap/150 mb/sec for full motion video) and allows large aggregate data carrying capacity (/spl ap/1000 mb/sec). The switch architecture is made extensible by adopting a network oriented design whereby the switch functions are cast with the requirements of a canonical network model for packet multicasting. The requirements are routing and priority based scheduling of packets from the input to output link(s) of each multicast channel segment supported by a switch. Packet routing is efficiently implementable in hardware by maintaining the information about all channel segments supported by the switch in a fast associative store. Our architecture yields high switching efficiency by using high speed link processors, distributed associative store, and parallel execution of routing and scheduling activities. The paper describes various functional elements of the switch architecture, and identifies the performance boundaries of switch realization on high speed processor and communication components.