Pipelined Non-strobed Sensing Scheme for Lowering BL Swing in Nano-scale Memories

Conventional strobed sense amplifiers (SA) have a fixed offset that dictates the minimum BL droop required during a memory read. BL droop is the major component of memory read delay and energy. In this paper we propose a novel non-strobed sensing scheme that can tradeoff BL droop with SA delay, allowing a memory to operate with lower BL droop, and thus lower energy. We demonstrate the sensing scheme on an 16KB SRAM. Lower BL swing results in 15% lower energy per read operation. The performance penalty due to higher SA delay is avoided by pipelining the SA delay into the next clock cycle. Thus, in addition to lower energy per read, a pipelined non-strobed SRAM is 52% faster than a conventional strobed SRAM and 26% faster than a pipelined strobed SRAM. This is the first work that demonstrates how BL droop can be traded-off with SA delay, enabling lower energy operation. We show the concept, circuit implementation, and simulation results in a commercial 45nm technology node.