A Test Pattern Generation Method Based on Fault Injection for Logic Elements of FPGA

Author

Yang, Chao ; Gao, Cheng ; Hong, Sheng ; Liang, Jian

Author_Institution

Dept. of Syst. Eng. of Eng. Technol., Beihang Univ., Beijing, China

fYear

2010

fDate

23-25 April 2010

Firstpage

1

Lastpage

4

Abstract

In this paper, we present a test pattern generation method based on fault injection for logic elements of FPGAs (Field Programmable Gate Arrays). This method is able to perform fault diagnosis for stuck-at-0 and stuck-at-1 faults, which can locate logic resource faults in the logic elements of FPGA. We use EP2C8Q208C8N´s LE (Logic Element) of Altera as the object to generate the test pattern, work out the test circuit and synthesis them by Quartus II. Finally, the test circuit is injected with stuck-at-0 and stuck-at-1 faults and the test patterns are generated by using SPICE.

Keywords

automatic test pattern generation; fault diagnosis; field programmable gate arrays; Altera; FPGA; Quartus II; fault diagnosis; fault injection; field programmable gate arrays; logic elements; stuck-at-0 faults; stuck-at-1 fault; test circuit; test pattern generation method; Circuit faults; Circuit synthesis; Circuit testing; Fault diagnosis; Field programmable gate arrays; Logic circuits; Logic testing; Programmable logic arrays; SPICE; Test pattern generators;

fLanguage

English

Publisher

ieee

Conference_Titel

Biomedical Engineering and Computer Science (ICBECS), 2010 International Conference on

Conference_Location

Wuhan

Print_ISBN

978-1-4244-5315-3

Type

conf

DOI

10.1109/ICBECS.2010.5462358

Filename

5462358