Optimized decimation filter architecture for 5th order ΣΔ converter in GSM/ UMTS/ Wi-max radio receiver

This paper presents an efficient design of a decimation filter for a continuous-time (CT) complex lowpass SigmaDelta modulator in multi-standard receiver. The proposed architecture fulfills the requirements of three standards: Wi-max, UMTS and GSM. The optimization of the proposed decimation structure leads to two implementation architectures which are optimized in different ways: area (in terms of used resources) and power consumption for the required throughput. Experimental results illustrate the high-speed data throughput and low-power consumption features of the proposed designs.