An Algorithm for Parallel Execution of Loops in Chip Multiprocessor Caches

Loops are predominant in computer programs. Data dependencies in loops dictate their execution time. An algorithm to execute loops in parallel based on the preordering of data in is presented in this paper. This algorithm can be applied to chip multiprocessors. The algorithm performs a fair share allocation of the loops to the available processors. Data accessed for loops accessed in a processor are fetched into its level one cache. The preordered data in the level one cache improve the performance of the cache. An example is simulated for the proposed algorithm and a performance improvement of 92% is observed in the overall execution time.