DocumentCode
2343391
Title
Path aware event scheduler in HoldAdvisor for fixing min timing violations
Author
Xiao, Tong ; Bagga, Harshinder ; Chen, George J. ; Cheung, Richard ; Pattipati, Raghu
Author_Institution
Microelectron. Group, Oracle America, Inc., Santa Clara, CA, USA
fYear
2011
fDate
9-12 Oct. 2011
Firstpage
71
Lastpage
77
Abstract
Min timing violations are fatal and need to be fixed in order to avoid chip failure. HoldAdvisor is used in chip design to find good locations for buffer insertion or swaps to assist in min timing fixing. Previously published work on buffer insertion has mainly focused on reducing delays to fix max timing violations. Those approaches cannot be directly applied to delay insertion for fixing min timing violations. A simple algorithm without considering path commonality has been used in HoldAdvisor. In this paper, we propose a novel approach to select nodes to fix min timing violations without causing new max timing violations. It dynamically computes the number of paths that can be fixed when a buffer is inserted or swapped at a particular location, and selects the node with the biggest gain. Compared to previous algorithms, it generates much better min timing solutions by making much fewer changes to a design.
Keywords
failure analysis; microprocessor chips; network synthesis; HoldAdvisor; buffer insertion; chip design; chip failure; delay insertion; min timing violations; path aware event scheduler; Algorithm design and analysis; Complexity theory; Delay; Heuristic algorithms; Libraries; Logic gates;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer Design (ICCD), 2011 IEEE 29th International Conference on
Conference_Location
Amherst, MA
ISSN
1063-6404
Print_ISBN
978-1-4577-1953-0
Type
conf
DOI
10.1109/ICCD.2011.6081378
Filename
6081378
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