Design of a Low Power Multiply-Accumulator for 2D Convolution in Video Processing Applications

Design of a low power multiply-and-accumulator (MAC) unit for video processing systems exploiting insignificant bits in pixels values and the similarity of neighboring pixels in video streams is presented in this paper. The proposed technique reduces dynamic power consumption by analyzing the bit patterns in the input data to reduce switching activities. Special values of the pixels in the video streams such as zero, one, repeated values or repeated bit combinations are detected and data paths in the architecture design are disabled appropriately to eliminate unnecessary switching in arithmetic units and data buses. It is observed that the proposed scheme helps to reduce operations and switching activities in the MAC unit up to 30% which results in lower power consumption with low hardware overhead