DocumentCode
2343822
Title
A new code-disjoint sum-bit duplicated carry look-ahead adder for parity codes
Author
Sogomonyan, E.S. ; Ocheretnij, V. ; Gössel, M.
Author_Institution
Dept. of Comput. Sci., Univ. of Potsdam, Germany
fYear
2001
fDate
2001
Firstpage
365
Lastpage
370
Abstract
A new code-disjoint self-checking carry look-ahead adder is proposed. To reduce the necessary area and the power dissipation only the sum bits of the adder cells are duplicated. This is possible since the input parity is determined by use of internal nodes of the adder cells. The adder is modeled by a SYNOPSIS CAD tool from the EUROCHIP-Project with a standard library. With respect to duplication and comparison the necessary area and the power dissipation can be reduced up to 38 % and up to 29 % respectively compared to an increase of the maximal delay of only 12 %
Keywords
adders; carry logic; circuit CAD; delays; logic CAD; low-power electronics; software libraries; EUROCHIP-Project; SYNOPSIS CAD tool; code-disjoint self-checking carry look-ahead adder; internal nodes; maximal delay; parity codes; power dissipation; standard library; sum bits; sum-bit duplicated adder; Computer errors; Computer science; Delay; Equations; Fault detection; Fault tolerance; Libraries; Parity check codes; Power dissipation; Signal design;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Symposium, 2001. Proceedings. 10th Asian
Conference_Location
Kyoto
ISSN
1081-7735
Print_ISBN
0-7695-1378-6
Type
conf
DOI
10.1109/ATS.2001.990310
Filename
990310
Link To Document