Multiple attractor cellular automata for hierarchical diagnosis of VLSI circuits

This paper uses the hierarchical structure of a VLSI circuit to design an efficient diagnosis scheme. A special class of non-group GF(2 ^p) CA referred to as multiple attractor cellular automata (MACH) is introduced to diagnose the faulty block of a circuit under test (CUT). The scheme employs significantly lesser memory and performs faster diagnosis than the existing methods reported so far. Experimental results validate the efficiency of the proposed scheme in terms of diagnostic resolution and execution speed along with significant reduction of memory