A 10-Gb/s CMOS clock and data recovery circuit with an analog phase interpolator

Author

Kreienkamp, Rainer ; Langmann, Ulrich ; Zimmermann, Christoph ; Aoyama, Takuma

Author_Institution

Lehrstuhl fur Integrierte Schaltungen, Ruhr-Univ., Bochum, Germany

fYear

2003

fDate

21-24 Sept. 2003

Firstpage

73

Lastpage

76

Abstract

A 10 Gb/s clock and data recovery (CDR) circuit for use in multi-channel applications is presented. The module comprises a binary phase detector, an analog phase interpolator, and a 1:4 demultiplexer. The prototype macro fabricated in a 0.11 μm CMOS technology consumes 220 mW. The active area is about 0.25×1.4 mm². The CDR fulfills the jitter tolerance requirements set by SDH/SONET with the test being based on a BER of 10^-12 and a PRBS of 2²³-1.

Keywords

CMOS integrated circuits; demultiplexing equipment; error statistics; integrated circuit design; interpolation; phase detectors; synchronisation; timing jitter; 0.11 micron; 0.25 mm; 1.4 mm; 10 Gbit/s; 220 mW; BER; CMOS CDR; PRBS; SDH; SONET; analog phase interpolator; binary phase detector; clock and data recovery circuit; demultiplexer; jitter tolerance requirements; multi-channel applications; CMOS analog integrated circuits; CMOS technology; Clocks; Detectors; Jitter; Phase detection; Prototypes; SONET; Synchronous digital hierarchy; Testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 2003. Proceedings of the IEEE 2003

Print_ISBN

0-7803-7842-3

Type

conf

DOI

10.1109/CICC.2003.1249362

Filename

1249362