A 10-Gb/s CMOS clock and data recovery circuit using a secondary delay-locked loop

Author

Rhee, Woogeun ; Ainspan, Herschel ; Rylov, Sergey ; Rylyakov, Alexander ; Beakes, Michael ; Friedman, Daniel ; Gowda, Sudhir ; Soyuer, Mehmet

Author_Institution

T. J. Watson Res. Center, Yorktown Heights, NY, USA

fYear

2003

fDate

21-24 Sept. 2003

Firstpage

81

Lastpage

84

Abstract

A 10 Gb/s clock and data recovery (CDR) circuit and a 1:4 DMUX are implemented in 0.12 μm CMOS. The CDR employs a secondary wideband delay-locked loop (DLL) to enable independent bandwidth control for jitter transfer and jitter tolerance. The proposed clock recovery and data recovery (CRDR) system enhances the jitter tolerance at high frequencies and offers less data-pattern-dependency for CDRs that use a binary phase detector.

Keywords

CMOS integrated circuits; delay lock loops; demultiplexing; integrated circuit design; phase detectors; synchronisation; timing jitter; 0.12 micron; 10 Gbit/s; CDR; CMOS; CRDR; DMUX; bandwidth control; binary phase detector; clock and data recovery circuit; data-pattern-dependency; jitter tolerance; jitter transfer; secondary delay-locked loop; wideband DLL; Band pass filters; Bandwidth; Circuits; Clocks; Delay; Jitter; Narrowband; Optical filters; Phase detection; Phase locked loops;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 2003. Proceedings of the IEEE 2003

Print_ISBN

0-7803-7842-3

Type

conf

DOI

10.1109/CICC.2003.1249364

Filename

1249364