Oxide charge trapping and HCI susceptibility of a submicron CMOS dual-poly (N+/P+) gate technology

Gate-oxide charge trapping and hot-carrier injection (HCI) susceptibility of a submicrometer CMOS dual-poly (n⁺/p⁺ ) gate, Ti-salicide, double-metal technology are discussed. The Si-SiO₂ interface property is believed to be modified by the p⁺ poly gate process, possibly due to boron penetration from the p⁺ polysilicon into the gate oxide. This accounts for the observed reduction in hole trapping during constant-current stress of the p⁺ poly gate capacitors and the large critical energy for interface trap generation during HCI stress of the p⁺ poly gate transistors. A general empirical relationship between the HCI power law parameters A (the precoefficient) and n (the power index) was obtained for both n-channel p-channel devices to describe the stress-time dependent degradation. Using the derived MOSFET lifetime, the limiting device type for this submicrometer CMOS dual-poly gate technology has also been determined