A 2-Gb/s/pin source synchronous CDMA bus interface with simultaneous multi-chip access and reconfigurable I/O capability

Author

Kim, Jongsun ; Xu, Zhiwei ; Chang, M. Frank

Author_Institution

Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA

fYear

2003

fDate

21-24 Sept. 2003

Firstpage

317

Lastpage

320

Abstract

A simultaneous reconfigurable multi-chip access bus interface for application in high-bandwidth multi-drop parallel interconnections such as a memory bus has been developed. The interface utilizes a source synchronous signaling and direct-sequence code-division multiple access (CDMA) technique for high bus concurrency and low channel latency. The prototype chip, fabricated in 0.18-μm CMOS and tested in a 10-cm test board achieves a data rate of 2 Gb/s/pin with multiple access and re-configurability between four (2-to-2) off-chip I/Os.

Keywords

CMOS integrated circuits; code division multiple access; interconnections; reconfigurable architectures; system buses; 10 cm; 2 Gbit/s; CDMA; CDMA bus interface; CMOS; bus concurrency; channel latency; direct-sequence code-division multiple access; high-bandwidth parallel interconnections; interface data rate; memory bus; multi-drop parallel interconnections; parallel bus interface; reconfigurable I/O capability; reconfigurable multichip access bus; simultaneous multichip access interface; source synchronous bus interface; synchronous signaling; Clocks; Code division multiplexing; Concurrent computing; Delay; Dielectric losses; Frequency; Integrated circuit interconnections; Multiaccess communication; Testing; Transceivers;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 2003. Proceedings of the IEEE 2003

Print_ISBN

0-7803-7842-3

Type

conf

DOI

10.1109/CICC.2003.1249411

Filename

1249411