Modeling and Evaluating the Scalability of Instruction Fetching in Superscalar Processors

Scalability is important in superscalar processors design. A superscalar processor is said to be linearly scalable if with linear increase in load or demand, performance remains constant relative to linear increase in resources. In this paper, for evaluating the instruction fetching scalability, an analytical model of a superscalar processor is proposed by defining the fetch unit as the "producer" of instructions and the execution unit as the "consumer". The scalability of the fetch unit relative to its branch predictor - the bi-mode predictor - is then evaluated using SPEC2000 suite of benchmarks. Our simulation results strongly suggest that reducing branch misprediction penalty is a better alternative solution - compared with increasing prediction accuracy - for improving instruction fetch scalability