A test structure for the measurement of fast internal signals in CMOS VLSI circuits

A test structure and a measurement method were developed allowing the analog measurement of fast signals at internal circuit nodes. The measurement method is based on the sampling principle. The test structure acts as a sampling probe integrated on chip. Attached to a circuit node, the probe imposes an additional load of only one minimum NMOS transistor gate. The test structure is clocked synchronously with the signal to be measured and converts the voltage for a fixed sampling point into a DC current. Successive DC measurements are taken while shifting the phase of the sampling clock relative to the system clock. The voltage signal is reconstructed by comparison of the sampled current values with reference values for a known input voltage