A novel matching network and design methodology for inductively degenerated LNAs at 60 GHz

A novel matching network and design methodology for the matching network of an inductively degenerated CMOS common source LNA at 60 GHz is presented in this paper. The design methodology minimizes the noise figure while guaranteeing the matching conditions. The new methodology depends on a developed theory in which the single ended LNA is divided into two identical parallel half sections, and the final output is the sum of these two section. The matching network is then viewed as a phase shifter with an optimum phase to cancel the noise of the other section. The design methodology is used to design an LNA using the 0.13μm CMOS technology. Simulations show a conversion gain (S21) of 28 dB, matching coefficient (S11) of -21.66 dB, minimum noise figure of 4.1 dB, and an IIP3 of -3.4 dBm. To our knowledge, the obtained NF is the best reported when compared to similar designs using the 0.13 μm technology node. The LNA consumes 12 mA from 2V supply.