• DocumentCode
    2347881
  • Title

    Model-based IDDQ pass/fail limit setting

  • Author

    Unni, T. Aruna ; Walker, D.M.H.

  • Author_Institution
    Xilinx Inc., San Jose, CA, USA
  • fYear
    1998
  • fDate
    12-13 Nov 1998
  • Firstpage
    43
  • Lastpage
    47
  • Abstract
    This paper describes several methods for setting LDDQ pass/fail limits using cell-based process, circuit and logic simulation. We demonstrate trade-offs in accuracy and model building effort on the ISCAS85 circuits
  • Keywords
    CMOS digital integrated circuits; circuit simulation; integrated circuit testing; logic simulation; logic testing; probability; CMOS ICs; IDDQ testing; ISCAS85 circuits; cell-based process; circuit simulation; dynamic method; logic simulation; model-based IDDQ pass/fail limit setting; probability method; worst case method; Circuit faults; Circuit simulation; Circuit testing; Computational modeling; Drives; Logic circuits; Production; Semiconductor device modeling; Switches; Temperature;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    IDDQ Testing, 1998. Proceedings. 1998 IEEE International Workshop on
  • Conference_Location
    San Jose, CA
  • Print_ISBN
    0-8186-9191-3
  • Type

    conf

  • DOI
    10.1109/IDDQ.1998.730731
  • Filename
    730731
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2347881