DocumentCode
2347924
Title
Clustering based identification of faulty ICs using IDDQ tests
Author
Jandhyala, Sri ; Balachandran, Hari ; Menon, Sankaran ; Jayasumana, Anura
Author_Institution
Texas Instrum. Inc., Dallas, TX, USA
fYear
1998
fDate
12-13 Nov 1998
Firstpage
48
Lastpage
52
Abstract
Technological advances in design and process have led to questions being raised about the applicability of IDDQ testing. The main concern is the inability to differentiate between normal and faulty quiescent currents in ICs. In this paper, we propose a new methodology aimed at addressing this concern through the application of clustering techniques to identify ICs with abnormal IDDQ values. Preliminary results of applying this technique in production test are also presented
Keywords
CMOS digital integrated circuits; fault diagnosis; integrated circuit testing; logic testing; production testing; CMOS; IDDQ tests; abnormal IDDQ values; clustering based identification; faulty ICs; logic testing; production test; quiescent currents; Application specific integrated circuits; CMOS integrated circuits; Condition monitoring; Fault detection; Fault diagnosis; Instruments; Leakage current; Logic devices; Logic testing; Process design;
fLanguage
English
Publisher
ieee
Conference_Titel
IDDQ Testing, 1998. Proceedings. 1998 IEEE International Workshop on
Conference_Location
San Jose, CA
Print_ISBN
0-8186-9191-3
Type
conf
DOI
10.1109/IDDQ.1998.730756
Filename
730756
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