A novel low-leakage 8T differential SRAM cell

Author

Sarfraz, Khawar

Author_Institution

Dept. of Electr. Eng., Lahore Univ. of Manage. Sci. (LUMS), Lahore, Pakistan

fYear

2011

fDate

3-5 Oct. 2011

Firstpage

19

Lastpage

24

Abstract

A novel low-leakage 8T differential SRAM cell is presented in 65nm bulk CMOS technology with the aim to address standby power consumption of embedded memories. The proposed cell supports differential read and write operation. HSPICE simulations incorporating process variation indicate that the proposed cell exhibits 84.8%, 44.8%, 42.6% and 27.0% less leakage under worst case conditions compared to 5T, 6T, 8T and 9T cells reported earlier in literature. With approximately 60% and 33% more area than the conventional 5T and the 6T cells and 11% less area than the 9T cell the proposed cell provides 3900.5× and 1.3× improvement in read static power noise margin compared to its 5T and 6T counterparts respectively under worst case conditions.

Keywords

CMOS memory circuits; SPICE; SRAM chips; low-power electronics; power consumption; CMOS; HSPICE simulation; differential read operation; differential write operation; embedded memory; low-leakage 8T differential SRAM cell; process variation; size 65 nm; standby power consumption; Inverters; Leakage current; Logic gates; Random access memory; Timing; Topology; Transistors; 8T SRAM cell; cache; differential; low-leakage; low-voltage; process variation; read-SNM-free;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI and System-on-Chip (VLSI-SoC), 2011 IEEE/IFIP 19th International Conference on

Conference_Location

Hong Kong

Print_ISBN

978-1-4577-0171-9

Electronic_ISBN

978-1-4577-0169-6

Type

conf

DOI

10.1109/VLSISoC.2011.6081624

Filename

6081624