Design and implementation of Costas loop based on FPGA

On the basis of analyzing the mathematical models of Costas loop, a method to model and simulate it by Simulink is put forward. In order to reduce the complexity of translating model to HDL (hardware description language), the model is realized by MATLAB code; the digital design of LPF (low-pass filter), LF (loop filter) and VCO (voltage-controlled oscillator) are mainly researched. At last, we accomplish the functional simulation by Verilog HDL code on Modlesim platform, finish the logic synthesis by synplify, and implement the hardware verification on the Cyclone series FPGA device EP1C6Q240C8 of Altera company. The final results are applied to the ASIC(application specific integrated circuit) design of BPSK (Binary Phase Shift Keying) signal´s demodulation. Results show that the Costas loop could correctly realize BPSK signal´s carrier recovery and data demodulation. Results of theoretical simulation and practical engineering experiments are the same. The method is proved simple, convenient and hardware resource saving.