DocumentCode
2348672
Title
Self-test method and recovery mechanism for high frequency TSV array
Author
Zhang, Jia ; Yu, Le ; Yang, Haigang ; Xie, Y.L. ; Zhou, F.B. ; Wang, Wei
Author_Institution
Inst. of Electron., Beijing, China
fYear
2011
fDate
3-5 Oct. 2011
Firstpage
260
Lastpage
265
Abstract
In this paper, through-silicon via (TSV) array in the form of one signal and four grounds (1S4G) are proposed to achieve high-frequency vertical connectivity for various three dimensional (3D) IC applications. Self-test method is developed to detect the conductor open and insulator short defects of TSV by capacitive and resistive measuring. Further a recovery mechanism for such a TSV array is introduced to enhance the TSV reliability. Test results will be configured to the TSV chain circuits by the central control logic and be used to determine the connection jumping between signal and redundant TSVs. This way, the failure TSVs could be replaced by the redundant ones. Simulation results demonstrate that the self-test circuit and central control logic could detect and recover the broken TSVs correctly. Moreover, the efficiency and area cost of the recovery mechanism is discussed, and it turns out that in a typical case of 96 signal TSVs, the chip yield could reach 90% with TSV failure rate equal to 5%, in exchange for less than 4% area cost of self-test circuit in the whole TSV area.
Keywords
automatic testing; integrated circuit interconnections; integrated circuit testing; radiofrequency integrated circuits; three-dimensional integrated circuits; capacitance measurement; conductor open defect; high frequency TSV array; high frequency vertical connectivity; insulator short defect; recovery mechanism; resistance measurement; self test method; three dimensional IC application; through silicon via array; Arrays; Built-in self-test; Resistance; Simulation; Three dimensional displays; Through-silicon vias; redundant TSV technique; scan chain; self-test; three dimensional (3D); through-silicon via (TSV); unit TSV block;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI and System-on-Chip (VLSI-SoC), 2011 IEEE/IFIP 19th International Conference on
Conference_Location
Hong Kong
Print_ISBN
978-1-4577-0171-9
Electronic_ISBN
978-1-4577-0169-6
Type
conf
DOI
10.1109/VLSISoC.2011.6081648
Filename
6081648
Link To Document