Assessment of III–V MOSFET architectures for low power applications using static and dynamic numerical simulation

Author

Shi, Ming ; Saint-Martin, Jércôme ; Bournel, Arnaud ; Querlioz, Damien ; Dollfus, Philippe ; Mo, Jiongjong ; Wichmann, Nicolas ; Desplanque, Ludovic ; Wallart, Xavier ; Danneville, Francois ; Bollaert, Sylvain

Author_Institution

IEF, Univ. Paris Sud, Orsay, France

fYear

2011

fDate

3-6 Oct. 2011

Firstpage

1

Lastpage

2

Abstract

To fulfill high-speed and low-power specifications for both logic and analog applications, III-V FETs with high-κ gate dielectric stack are especially appealing, in particular for their ability to operate under low power supply voltage. Using complementary tools such as a 2D Poisson-Schrödinger solver and a Monte Carlo device simulator, we assess the potentiality of several III-V MOSFET structures in terms of gate charge control, static/dynamic performance and noise.

Keywords

III-V semiconductors; MOSFET; Monte Carlo methods; high-k dielectric thin films; low-power electronics; semiconductor device models; stochastic processes; III-V MOSFET architectures; analog applications; dynamic numerical simulation; gate charge control; high gate dielectric stack; high speed specifications; logic applications; low power applications; low power specifications; static numerical simulation; Aluminum oxide; Capacitance-voltage characteristics; Cutoff frequency; Gain; HEMTs; Logic gates; Quantum capacitance;

fLanguage

English

Publisher

ieee

Conference_Titel

SOI Conference (SOI), 2011 IEEE International

Conference_Location

Tempe, AZ

ISSN

1078-621X

Print_ISBN

978-1-61284-761-0

Electronic_ISBN

1078-621X

Type

conf

DOI

10.1109/SOI.2011.6081701

Filename

6081701