FPGA based architecture evaluation of cryptographic coprocessors for smartcards

Author

Ploog, Hagen ; Timmermann, Dirk

Author_Institution

Inst. of Appl. Microelectron. & Comput. Sci., Rostock Univ., Germany

fYear

1998

fDate

15-17 Apr 1998

Firstpage

292

Lastpage

293

Abstract

In 1996, about 600 million IC cards were manufactured worldwide. Due to very small die sizes (max. 25 mm²) smartcards encounter more severe restrictions than conventional coprocessors. We study coprocessor architectures for very fast but area efficient modular exponentiation (FME) based on Montgomery multiplication. For assessment purposes we developed an evaluation board containing a 8051 microprocessor, a XILINX FPGA and RAM with variable bus width (8b to 32b). We evaluated these architectures in terms of the main design parameters to ease design decisions for smartcards in arbitrary technologies

Keywords

coprocessors; cryptography; digital arithmetic; field programmable gate arrays; smart cards; 8051 microprocessor; FPGA based architecture evaluation; IC cards; Montgomery multiplication; XILINX FPGA; arbitrary technologies; area efficient modular exponentiation; coprocessor architectures; cryptographic coprocessors; design decisions; design parameters; die sizes; evaluation board; smartcards; variable bus width; Arithmetic; Clocks; Coprocessors; Cryptography; Field programmable gate arrays; Manufacturing; Microprocessors; Power system security; Read-write memory; Writing;

fLanguage

English

Publisher

ieee

Conference_Titel

FPGAs for Custom Computing Machines, 1998. Proceedings. IEEE Symposium on

Conference_Location

Napa Valley, CA

Print_ISBN

0-8186-8900-5

Type

conf

DOI

10.1109/FPGA.1998.707922

Filename

707922