• DocumentCode
    2350390
  • Title

    Statistical MOS VLSI circuit optimization with non-nested experimental design

  • Author

    Yu, T.K. ; Kang, S.M.

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Illinois Univ., Urbana, IL, USA
  • fYear
    1988
  • fDate
    7-9 June 1988
  • Firstpage
    1799
  • Abstract
    The authors present an efficient method that minimizes the circuit performance sensitivities to the MOSFET parameter fluctuations. A worst-case and squared-error loss function is used to evaluate the noise sensitivity of a design. The statistical circuit performance is modeled as a function of both the transistor channel widths and a noise parameter, and circuit simulation points are selected by an experimental design strategy that assumes no experimental errors. The fitted performance model is then used to predict and optimize the worst-case performance and the squared-error loss function. Compared with the method of G. Taguchi and Y. Wu (1985) in two circuit examples, the proposed method requires about 60% fewer circuit simulations and predicts the loss functions with comparable or better accuracy.<>
  • Keywords
    MOS integrated circuits; VLSI; circuit CAD; sensitivity analysis; statistical analysis; MOS VLSI circuit optimisation; accuracy; circuit simulations; noise sensitivity; non-nested experimental design; squared-error loss function; statistical circuit performance; transistor channel widths; worst-case performance; Circuit noise; Circuit optimization; Circuit simulation; Computer errors; Design for experiments; Design methodology; Fluctuations; MOSFET circuits; Performance loss; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 1988., IEEE International Symposium on
  • Conference_Location
    Espoo, Finland
  • Type

    conf

  • DOI
    10.1109/ISCAS.1988.15285
  • Filename
    15285