DocumentCode
2351607
Title
Logical effort based technology mapping
Author
Karandikar, Shrirang K. ; Sapatnekar, Sachin S.
Author_Institution
Dept. of Electr. & Comput. Eng., Minnesota Univ., Minneapolis, MN, USA
fYear
2004
fDate
7-11 Nov. 2004
Firstpage
419
Lastpage
422
Abstract
We propose a new approach to library-based technology mapping, based on the method of logical effort. Our algorithm is close to optimal for fanout-free circuits, and is extended to solve the load-distribution problem for circuits with fanout. On average, benchmark circuits mapped using our approach are 25.39% faster than the solutions obtained from SIS.
Keywords
circuit optimisation; integrated circuit design; load distribution; logic design; circuit mapping; fanout-free circuits; library-based technology mapping; load-distribution problem; logical effort; Circuit synthesis; Contracts; Delay effects; Delay estimation; Equations; Libraries; Load modeling; Logic circuits; Noise measurement; Parasitic capacitance;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer Aided Design, 2004. ICCAD-2004. IEEE/ACM International Conference on
ISSN
1092-3152
Print_ISBN
0-7803-8702-3
Type
conf
DOI
10.1109/ICCAD.2004.1382611
Filename
1382611
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