5Gbits/sec, 300mV Precharge, 256b, Low Power Rhythmic SRAM

Effective design of cache SRAM has always been the challenging task in embedded systems dedicated to image processing applications such as vector quantizer (VQ). The low power high speed SRAM array is the need of VQ. The mathematical model and simulation results for low power, high speed, fault tolerant codebook SRAM is presented in this paper. The cell, precharge, transmission logic, sense amplifier, redundant bits and IOs are modeled and SPICE simulated. Since the codebook has rhythmic nature, the successive multiple read cycles are important than write. The implementation is done at 0.25 mum technology. The results show that the least precharge is at 300 mV. The array operates minimum at 600 mV. The dissipation of 256 b array is 1.8 mW at read speed of 5 Gbits/sec at precharge of 1.25 V and supply of 2.5 V.