Analysis and evaluation of a hybrid interconnect structure for FPGAs

In this paper, a cluster-based FPGA is proposed. The proposed FPGA has a hybrid interconnect structure which takes advantages of both mesh and tree topologies. We analyze the area and performance of proposed FPGA in terms of the needed switches by comparing with those of conventional FPGAs. We evaluate the proposed architecture on a series of benchmark designs. The experimental results show that the proposed model can significantly reduce the routing area, achieve high performance and admit more implementations of various designs at the price of a modest increase of switches required for that architecture.