DocumentCode
2355018
Title
Power distribution system for JEDEC DDR2 memory DIMM
Author
Smith, Larry D. ; Lee, Jeffery
Author_Institution
Sun Microsystems, Inc., Menlo Park, CA, USA
fYear
2003
fDate
27-29 Oct. 2003
Firstpage
121
Lastpage
124
Abstract
The Power Distribution System (PDS) for a JEDEC DDR2 Dual Inline Memory Module (DIMM) has been designed. The process involved establishing a target impedance in the frequency domain, determining the inductance of the connector and capacitor mounts and selecting a matrix of discrete ceramic capacitors from a menu of previously characterized devices to meet the target impedance. After hardware was available, S21 measurements were made with a 2 port VNA to establish model to hardware correlation.
Keywords
SPICE; capacitance; ceramic capacitors; frequency-domain analysis; inductance; integrated circuit packaging; integrated memory circuits; multichip modules; power supply circuits; 2-port VNA; JEDEC DDR2 dual inline memory module; SPICE simulation; capacitor mounts; connector mounts; discrete ceramic capacitors; frequency domain; inductance; power distribution system; target impedance; Capacitance; Capacitors; Conductors; Connectors; Frequency; Impedance; Inductance; Power distribution; Power supplies; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Electrical Performance of Electronic Packaging, 2003
Conference_Location
Princeton, NJ, USA
Print_ISBN
0-7803-8128-9
Type
conf
DOI
10.1109/EPEP.2003.1250013
Filename
1250013
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