• DocumentCode
    2355222
  • Title

    A fast, numerical circuit-level model of carbon nanotube transistor

  • Author

    Kazmierski, Tom J. ; Zhou, Dafeng ; Al-Hashimi, Bashir M.

  • Author_Institution
    Sch. of Electron. & Comput. Sci., Southampton Univ., Southampton
  • fYear
    2007
  • fDate
    21-22 Oct. 2007
  • Firstpage
    33
  • Lastpage
    37
  • Abstract
    Recently proposed circuit-level models of carbon nanotube transistor (CNT) for SPICE-like simulators suffer from numerical complexities as they rely on numerical evaluation of integrals or internal Newton-Raphson iterations to find solutions of non-linear dependencies or both. Recently an approach has been proposed which eliminates the need for numerical integration when calculating the charge densities in CNT through the use of piece-wise linear approximation. This paper extends the effective employment of numerical piece-wise approximation to the solution of the Fermi-Dirac integral to accelerate the CNT model speed when evaluating the source-drain current while maintaining high modeling accuracy. Our results show a speed up of more than three orders of magnitude compared with the theoretical CNT model implemented in FETToy, used as a reference for verifying newer models. Comparisons of drain-source current characteristics of the new model against that in FETToy are presented, confirming that the accuracy of the proposed approach is maintained within less than 5% in terms of RMS error.
  • Keywords
    Newton-Raphson method; SPICE; approximation theory; carbon nanotubes; fermion systems; field effect transistors; nanotube devices; piecewise linear techniques; quantum statistical mechanics; CNT; FETToy; Fermi-Dirac integral; SPICE-like simulator; carbon nanotube transistor; field effect transistor; internal Newton-Raphson iteration; numerical circuit-level model; piecewise linear approximation; source-drain current characteristics; Carbon nanotubes; Circuit simulation; Energy states; Integral equations; Mathematical model; Neodymium; Numerical models; Piecewise linear techniques; Transistors; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Nanoscale Architectures, 2007. NANOSARCH 2007. IEEE International Symposium on
  • Conference_Location
    San Jose, CA
  • Print_ISBN
    978-1-4244-1790-2
  • Electronic_ISBN
    978-1-4244-1791-9
  • Type

    conf

  • DOI
    10.1109/NANOARCH.2007.4400855
  • Filename
    4400855