DocumentCode
2356267
Title
The design of decoders for Q-valued logic circuits
Author
Prieto, A. ; Martin-Smith, P. ; Pelayo, F. ; Lloris, A.
Author_Institution
Dept. of Electron. & Syst. Inf., Granada Univ., Spain
fYear
1988
fDate
0-0 1988
Firstpage
32
Lastpage
39
Abstract
A design procedure is presented for multivalued threshold decoders using only three very simple modules. This general design method can be used in any technology, either in voltage or in current mode. The resulting decoders can easily be included in integrated circuits using standard integration techniques. The procedure is applied, as an example, to the design of a quaternary decoder in CMOS technology.<>
Keywords
CMOS integrated circuits; decoding; integrated logic circuits; logic design; many-valued logics; CMOS technology; Q-valued logic circuits; design; multivalued threshold decoders; CMOS technology; Circuit synthesis; Decoding; Design methodology; Integrated circuit synthesis; Integrated circuit technology; Inverters; Logic circuits; Logic design; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Multiple-Valued Logic, 1988., Proceedings of the Eighteenth International Symposium on
Conference_Location
Palma de Mallorca, Spain
Print_ISBN
0-8186-0859-5
Type
conf
DOI
10.1109/ISMVL.1988.5145
Filename
5145
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