Estimation of maximum temperature in 3D-integrated package by thermal network method

In the dream chip project of ASET, a 3D-integrated package is developed. The chip has multi layered structure and heat generation density in the chip becomes much larger than conventional single layered chip. Therefore, thermal design, which is temperature management, of the chip is very important. The dream chip has complex structure and there exist so many parameters for thermal design. If we try to apply normal CFD (Computational Fluid Dynamics) to the parameter survey study of the chip, it takes long computational time. In this study, we applied thermal network analysis to the thermal design of the chip. Thermal network method is much faster than CFD and this method is very useful from the viewpoint of the parametric study. The results show that higher thermal conductivity material of the inter-chip-fill (the underfill resin between wafers) or more than 10 % of the interconnection area is required for the temperature management of the chip.